Prof. Choi`s R.P.

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  • 21 J.‐H. Ahn, J.‐Y. Kim, C. Jung, D.‐I. Moon, S.‐J. Choi, C.‐H. Kim, K.‐B. Lee, H. G. Park, and Y.‐K. Choi "CMOS-Based Biosensors with an Independent Double‐Gate FinFET" IEEE International Electron Device Meeting (IEDM), 2011-12 PDF
  • 20 D.‐I. Moon, J.‐S. Oh, S.‐J. Choi, S. Kim, J.‐Y. Kim, M.‐S. Kim, Y.‐S. Kim, M.‐H. Kang, J.‐W. Kim, and Y.‐K. Choi "Multi‐Functional Universal Device using a Band‐Engineered Vertical Structure" IEEE International Electron Device Meeting (IEDM), 2011-12 PDF
  • 19 M. Lim, S.‐J. Choi, K. Moon, E. Jung, M.‐L. Seol, Y. Do, Y.‐K. Choi, and H. Han "Terahertz Time Domain Spectroscopy of Vertical Silicon Nanowires" 36th International Conference on Infrared, Millimeter, and Terahertz Waves, 2011-10 PDF
  • 18 D. J. Baek, S.‐J. Choi, D.‐I. Moon, and Y.‐K. Choi "Scaling of the Pull‐In Voltage in a Novel CMOS‐compatible NEMS Switch" Solid State Devices and Materials (SSDM), 2011-09 PDF
  • 17 S. Kim, S.‐J. Choi, D.‐I. Moon, and Y.‐K. Choi "Optical‐Charge Pumping: A Universal Trap Characterization Technique for Nanoscale Floating Body Devices" Symposium on VLSI Technology Digest of Technical Papers (VLSI), pp. 190‐191, 2011-06 PDF
  • 16 S.‐J. Choi, D.‐I. Moon, J. P. Duarte, S. Kim, and Y.‐K. Choi "A Novel Junctionless All‐Around‐Gate SONOS Device with a Quantum Nanowire on a Bulk Substrate for 3D Stack NAND Flash Memory" Symposium on VLSI Technology Digest of Technical Papers (VLSI), pp. 74‐75, 2011-06 PDF
  • 15 D.‐I. Moon, S.‐J. Choi, C.‐J. Kim, J.‐Y. Kim, J.‐S. Lee, J.‐S. Oh, G.‐S. Lee, Y.‐C. Park, D.‐W. Hong, D.‐W. Lee, Y.‐S. Kim, J.‐W. Kim, J.‐W. Han, and Y.‐K. Choi "Ultimately Scaled 20nm Unified‐RAM" IEEE International Electron Device Meeting (IEDM), 12.2, pp. 284‐287, 2010-12 PDF
  • 14 S.‐J. Choi, D.‐I. Moon, Y. Ding, E. Y. J. Kong, Y.‐C. Yeo, and Y.‐K. Choi "A Novel Floating Body Cell Memory with Laterally Engineered Bandgap using Si‐Si:C Heterostructure" IEEE International Electron Device Meeting IEDM), 22.4, pp. 532‐555, 2010-12 PDF
  • 13 S.‐J. Choi, J.‐W. Han, S. Kim, D.‐I. Moon, M. Jang, and Y.‐K. Choi "A Novel TFT with a Laterally Engineered Bandgap for 3D Logic and Flash Memory" Symposium on VLSI Technology Digest of Technical Papers (VLSI), pp. 111‐112, 2010-06 PDF
  • 12 M. Jang, M. Jun, Y.‐K. Choi, and S.‐J. Choi "Metal source/drain technology for nanoscale MOSFET & high speed flash applications" Semicon Korea 2010, 2010-02 PDF
  • 11 D.‐I. Moon, S.‐J. Choi, J.‐W. Han, and Y.‐K. Choi "A Study of a BJT based capacitorless 1T‐DRAM with Consideration of Geometrical Dependence" Proceedings of the 17th Korean Conference on Semiconductors, pp. 7‐8, Daegu, 2010-02 PDF
  • 10 Y.‐K. Choi, M. Jang, and S.‐J. Choi "High speed Flash Memory by a Dopant‐Segregated Schottky‐Barrier MOSFET" 2009 Bulletin of the Korean Physical Society, pp. 191, 2009-10 PDF
  • 9 S.‐J. Choi, J.‐W. Han, S. Kim, D.‐I. Moon, M. Jang, J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y.‐K. Choi "Performance Breakthrough in NOR Flash Memory with Dopant‐Segregated Schottky‐Barrier (DSSB) SONOS Devices" Symposium on VLSI Technology Digest of Technical Papers (VLSI), pp. 222‐223, 2009-06 PDF
  • 8 J.‐W. Han, S.‐W. Ryu, S. Kim, C.‐J. Kim, J.‐H. Ahn, S.‐J. Choi, K. J. Choi, B. J. Cho, J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y.‐K. Choi "Gate‐All‐Around Silicon Nanowire MOSFETs on Bulk Substrate" Proceedings of the 16th Korean Conference on Semiconductors, 2009-02 PDF
  • 7 S.‐J. Choi, S.‐W. Ryu, J.‐W. Han, S. Kim, and Y.‐K. Choi "A Novel Capacitorless DRAM Operated by Gate‐Induced Drain‐Leakage (GIDL) for Improved Sensing Window and Low Power Operation" Proceedings of the 16th Korean Conference on Semiconductors, pp. 62-63, 2009-02 PDF
  • 6 S.‐J. Choi, J.‐W. Han, S. Kim, D.‐H. Kim, M. Jang, J.‐H. Yang, J. S. Kim, K. H. Kim, J. S. Oh, M. H. Song, G. S. Lee, Y. C. Park, J. W. Kim, and Y.‐K. Choi "High Speed Flash Memory and 1T‐DRAM on Dopant Segregated Schottky Barrier (DSSB) FinFET SONOS for Multi‐functional SoC applications" IEEE International Electron Device Meeting (IEDM), 6.5, pp. 223‐226, 2008-12 PDF
  • 5 J.‐W. Han, S.‐W. Ryu, S. Kim, C.‐J. Kim, J.‐H. Ahn, S.‐J. Choi, K. J. Choi, B. J. Cho, J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y.‐K. Choi "Energy Band Engineered Unified‐RAM (URAM) for Multi‐Functioning 1T‐DRAM and NVM" IEEE International Electron Device Meeting (IEDM), 6.6, pp. 227‐230, 2008-12 PDF
  • 4 S.‐J. Choi, J.‐W. Han, S. Kim, C.‐J. Choi, M. Jang, and Y.‐K. Choi "Current Flow Mechanism in Schottky‐Barrier MOSFETs and Application to the 1T‐DRAM" Solid State Devices and Materials (SSDM), pp. 226‐227, 2008-09 PDF
  • 3 J.‐Woo Han, S.‐W. Ryu, S. Kim, C.‐J. Kim, J.‐H. Ahn, S.‐J. Choi, K. J. Choi, B. J. Cho, J. S. Kim, K. H. Kim, J. S. Oh, M. H. Song, G. S. Lee, Y. C. Park, J. W. Kim, and Y.‐K. Choi "Band offset FinFET‐Based URAM (Unfied‐RAM) Built on SiC for Multi‐Functioning NVM and Capacitorless DRAM" Symposium on VLSI Technology Digest of Technical Paper (VLSI), 20.3, pp. 200‐201, 2008-06 PDF
  • 2 S.‐J. Choi, J.‐W. Han, S.‐W. Ryu, S. Kim, and Y.‐K. Choi "A Comprehensive Modeling of Threshold Voltage with Consideration of Body Doping Concentration and Body Thickness in Double‐Gate FinFETs" Proceedings of the 15th Korean Conference on Semiconductors, 2008-02 PDF